1. Field of the Invention
This invention relates to a digital phase lock loop. More particularly it relates to a phase lock loop in which the effective loop gain and bandwidths are varied in accordance with the frequency/phase error.
2. Background Information
The invention is directed to digital phase lock loops commonly incorporated in large-scale integrated circuits. The operations performed by these circuits are synchronized to the output of a local clock and the clock in turn is often synchronized to an external reference clock so as to synchronize the operations of the circuit to those of other devices in a system that includes the circuit. To accomplish the latter synchronization the local clock is configured as a voltage-controlled oscillator (VCO) whose output is compared with the external reference signal in a frequency/phase detector. The output of the detector is an error signal that is applied to a low-pass filter that serves as an error integrator. The output of the filter drives the VCO.
The bandwidth (and the related time constant) of the filter is often a compromise between two conflicting requirements. Specifically, when the frequency/phase error of the local oscillator is large, a short filter time constant is desirable so that the filter output rapidly reflects changes in the error signal, thereby facilitating rapid adjustment (or acquisition) of the oscillator frequency with respect to the reference signal. On the other hand, when the oscillator output is close to the frequency and phase of the reference, a long time constant is desirable in order to provide loop stability and immunity from noise and other short-term perturbations.
It has been suggested that the filter bandwidth can be changed in accordance with the magnitude of the frequency/phase error. Specifically, different resistors or capacitors can be switched into or out of the filter to provide a large or narrow bandwidth or narrow bandwidth as desired. However, the switching of components into and out of the filter circuit is a source of undesirable noise in the filter output, resulting from the sudden change in filter parameters perturbations and noise coupled through the typically used MOSFET switch that connects or disconnects these components.
Other prior art attempts may be found in U.S. Pat. Nos.: 6,504,437 ('437); 6,476,681 ('681); 5,942,949 ('949); and 5,675,292 ('292). The '437 patent is entitled, “Low-noise Fast Lock Loop with Gearshifting Control,” and discloses switching filter components. The '681 patent is entitled, “Adjustable Bandwidth PLL with Fast Settling Time,” and switches in additional filter components. The '949 patent is entitled, “Self Calibrating PLL with Auto Trim Operations for Selecting Oscillator Operative Curve,” and discloses changing the VCO gains along with filter components. The '292 patent is entitled, “PLL Enabling Smooth Loop Bandwidth Switching over a Wide Range,” and also switched filter components that change current sources into voltage sources to control bandwidth. These U.S. patents are incorporated herein by reference.
It is an objective of the present invention to provide for a fast acquisition lock of the VCO to a references frequency signal without compromising system stability or introducing switching noise.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.